(1) Field of the Invention
This invention relates to methods of forming high capacitance capacitors for DRAM circuits and more specifically to the use of a first rapid thermal anneal to form titanium silicide and a second rapid thermal anneal to form titanium silicide agglomerates followed by selective etching of exposed polysilicon to increase the surface area of a capacitor plate.
(2) Description of the Related Art
U.S. Pat. No. 5,182,232 to Chhabra et al. describes a method of forming a texturized surface by annealing, oxidizing, and etching a layer of metal silicide that has been deposited on a semiconductive material. This method uses a first anneal to form metal silicide but does not use a second anneal.
U.S. Pat. No. 5,110,752 to Lu describes a method of forming a capacitor plate by depositing a refractory metal over a polysilicon layer. The composite is heated to form metal silicide and a roughened surface. The metal silicide is then removed to form a roughened surface to form a first capacitor plate. The method uses a first anneal but does not use a second anneal.
U.S. Pat. No. 5,256,587 to Jun et al. describes a method of forming a capacitor using hemispherical grain polysilicon for a first capacitor plate. The polysilicon surface with hemispherical grain polysilicon is selectively etched to increase the surface area.
U.S. Pat. No. 5,498,558 to Kapoor describes a method of forming an integrated circuit structure with a floating gate electrode. The method involves forming a thin layer of silicide forming metal over a polysilicon layer and heating sufficiently to react all the metal with polysilicon to form metal silicide and to coalesce the metal silicide into a discontinuous layer on the polysilicon. A capacitor is not formed.
U.S. Pat. No. 5,583,070 to Liao et al. describes a method of forming a capacitor using hemispherical grain polysilicon to increase the surface area of a capacitor plate.